Arkane Works №05 · Archived Record

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Nanoelectronics Ultrasonic NDT

An ultrasonic non-destructive testing workflow for finding defects in 10 µm-pitch Cu–Cu hybrid bonds — the interconnects underneath advanced chiplet packaging. Direct simulation at that scale defeats standard NDT tooling, so the work develops a scaling transform: grow the geometry by k = 1000, drop frequency from 1 GHz to 1 MHz, and preserve the d/λ ratio (~7.14) so the wave physics carries over exactly. Conducted at ASU's Celano Lab, where the CAD models supported two lab research publications.

Bond Pitch10 µm
Scale Factork = 1000
Frequency1 GHz → 1 MHz
Invariantd/λ ≈ 7.14
Scaling Model.02

Models are built in SolidWorks and solved in CIVA NDT, simulating scanning acoustic microscopy with wave propagation (∂²u/∂t² = c²∇²u) through the scaled bond stack at 10 µm-equivalent resolution. The transform sidesteps CIVA's microscale viewport limits entirely, turning setups that fought the software into fast iterations for SAM inspection planning.

Wave Physics.03

The scaling holds only if the physics does. Reflection coefficients R = (Z₂−Z₁)/(Z₂+Z₁) are invariant under the transform; material properties (Cu at ρ = 8700 kg/m³, water coupling) were validated against literature; and transducer focal geometry was re-derived at scale to keep beam behavior faithful. Material nonlinearity (σ = Eε + βε²) is the main fidelity limit being worked, handled with higher-order wave equations.

Failure Analysis.04

In parallel, a comprehensive literature review of Cu–Cu hybrid bonding failure mechanisms mapped the defect landscape the simulations target: thermal-mechanical stresses from CTE mismatch, warpage, voids, and delamination in 3D stacks. That work extended into a technical presentation on through-silicon vias and interposer design for heterogeneous integration — the same solid mechanics, applied from nanoscale to aerospace structures.

Validation & Application.05

Scaled CIVA results resolve voids and delaminations at dimensions equivalent to the 10 µm pitch, correlating with microscale reference models; ongoing validation compares simulated C-scans against physical SAM data on industry chiplet samples. The payoff is QA throughput for 3D packaging — the reliability bottleneck for AI and high-performance silicon — and the workflow generalizes to finer pitches and other NDT modalities.

References.06